Verilog Code For Serial Adder Subtractor Using Logic Gates
Adder/Subtractor An adder/subtractor is an arithmetic circuit which can add/subtract two N-bit binary numbers and output their N-bit binary sum/difference,. Half Adder Module in VHDL and Verilog. Half adders are a basic building block for new digital designers. A half-adder shows how two bits can be added together with a few simple logic gates.In practice they are not often used because they are limited to two one-bit inputs.
The serial binary adder or bit-serial adder is a digital circuit that performs binaryaddition bit by bit. The serial full adder has three single-bit inputs for the numbers to be added and the carry in. There are two single-bit outputs for the sum and carry out. The carry-in signal is the previously calculated carry-out signal. The addition is performed by adding each bit, lowest to highest, one per clock cycle.
Serial binary addition[edit]
Serial binary addition is done by a flip-flop and a full adder. The flip-flop takes the carry-out signal on each clock cycle and provides its value as the carry-in signal on the next clock cycle. After all of the bits of the input operands have arrived, all of the bits of the sum have come out of the sum output.
Serial binary subtracter[edit]
The serial binary subtracter operates the same as the serial binary adder, except the subtracted number is converted to its two's complement before being added. Alternatively, the number to be subtracted is converted to its ones' complement, by inverting its bits, and the carry flip-flop is initialized to a 1 instead of to 0 as in addition. The ones' complement plus the 1 is the two's complement.
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Example of operation[edit]
- X=5, Y=9, Sum=14
- Binary
- 0101+1001=1110
- Addition of each step
| Inputs | Outputs | |||
|---|---|---|---|---|
| Cin | X | Y | Sum | Cout |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 0 | 1 | 1 | 0 |
Msi star type es500w drivers for mac. *addition starts from lowest
- Result=1110 or 14
See also[edit]
References[edit]
Further reading[edit]
External links[edit]
- Interactive Serial Adder[dead link], Provides the visual logic of the Serial Adder circuit built with Teahlab's Simulator.
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Homework Statement
My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module.
I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits:
Inputs for the shift register are: Si, CLK, Reset
Outputs for the shift register are: So, D7 through D0 (one for each bit of the register)
Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful.